1. Field of the Invention
The present invention relates to programmable delay units and more particularly to providing a dual edge programmable delay unit.
2. Description of Related Art
U.S. Pat. No. 5,933,039 of Hui et al (Hui '039) for “Programmable Delay Line” is related to a voltage comparator-RS register based delay line. The signal chain is long, with a minimum delay as long as 5 nanoseconds (ns). Thus the delay line of Hui '039 cannot be used in a high-speed circuit. The rising edge and the falling edge have the same delay time, so it cannot be used as an on-chip timing adjusting unit. The current source is amplifier-resistor based, and the setting time is quite long depending on the resistance selected and the parasitic capacitance. The delay line operation of Hui '039 is “reset signal” based; and no program code protection function is provided, so it cannot be used in a real time and an on-chip operation. Therefore the delay line units of the Hui et al is related to a different application field and different circuit structure from those of present invention.
U.S. Pat. No. 5,355,038 of Hui et al (Hui '038) for “Architecture for Programmable Delay Line Integrated Circuit” is similar to Hui '039 in terms of the concepts and the system structure, but the circuit implementation is somewhat different. The delay line is based on a voltage-comparator and an RS register. The minimum delay line is long, 10 ns, so it cannot work in high speed circuits. The rising edge and the falling edge cannot have separate delay settings, so it cannot be used as a on-chip timing adjustment unit. With an amplifier-resistor based current source, the setting time is quite long, depending on the resistance selected and the parasitic capacitance. The delay line operation of Hui '038 is “reset signal” based and there is no program code protection function, so it cannot be used in a real time and on-chip operation. Therefore, the delay line units of Hui '038 are related to a different application field and a different circuit structure from the present invention.
U.S. Pat. No. 5,936,451 of Phillips entitled “Delay Circuit and Method” describes a delay line related to very low speed applications such as power motors, solenoids, which is an entirely different field from that of present invention. The main purposes of the Phillips patent are to avoid turning on the NFET and the PFET at the same time when they are staked between power supply and ground. The goal of the Phillips patent is to obtain long delays without requiring a large capacitor or a large resistor, which is a completely different purpose and goal from those of present invention. The delay circuit of the Phillips patent has no capability to set different delay times for rising edge and falling edge independently. Therefore the concept, the purpose and the function of the delay circuit in the patent are different from those of present invention.
U.S. Pat. No. 6,124,745 of Hilton entitled “Delay and Interpolation Timing Structures and Methods” describes a delay circuit based on a differential amplifier with two capacitors. The circuit structure and operation principle are completely different from those of present invention. The delay circuit of the Hilton patent has no capability to set different delay times of the rising edge and the falling edge separately. Therefore the circuit structure, operation principle and the function of the delay line in the Hilton patent are different from those of present invention.
FIG. 1 shows a schematic circuit diagram of a conventional prior art programmable delay unit 10 of a type that is used widely in industry currently. The delay unit consists of “n” inverter-based delay elements IP1, IP2, . . . , IPn in series, a series connected set of “n” transmission gates TG1, TG2, . . . , TGn−1, TGn and an “n” bit latch 27. Inverter-based delay element IP1, that includes series connected inverters 14 and 16, receives an input signal IN on input line 12 and provides a delayed output which is connected via node 17 to the source/drain circuit of transmission gate TG1, as well as the input of inverter 18. Inverter-based delay element IP2, which includes series connected inverters 18 and 20, has its input connected to node 17 and has its output connected via node 21 to the source/drain circuit of transmission gate TG2, as well as the input of the next inverter not shown through node 21. Farther along near the end of the delay unit 10 is a node 23 connected to the source drain circuit of transmission gate TGn−1. The final inverter-based delay element IPn in the programmable delay unit 10, which includes series connected inverters 24 and 26, has its input connected to node 23 and has its output connected to the source/drain circuit of transmission gate TGn. The source/drain circuits of the transmission gates TG1, TG2, . . . , TGn−1, TGn are connected to the node 22 and output line 29. The latch 27 provides an turn ON signal to a selected one of the lines L1, L2, . . . , Ln−1 and Ln to the gate electrode of a corresponding one of the “n” transmission gates TG1, TG2, . . . TGn−1, TGn as a function of the control word on bus line 28.
When the control word on control word bus 28 is latched into the latch 27, one of the transmission gates TG1, TG2, . . . TGn−1, TGn is selected, i.e. turned on, and the corresponding output of one of the delay elements IP1, IP2, . . . , IPn is selected to be connected through one of the source drain circuits of the selected transmission gates TG1, TG2, . . . , TGn−1, TGn via node 22 to and through the output line 29 to provide the output signal OUT.
The problem with the kind of delay unit illustrated by FIG. 1 is that the rising edge delay time and the falling edge delay time are not set separately. Usually, the two delay times of each delay element are not the same. The result is that delay time differences are accumulated when more than one of the delay elements in series is selected. Thus the problem is that pulse width distortion occurs in the input pulse and the output pulse from the type of circuit shown in FIG. 1.